Numerical investigation on optimal arrangement of IC chips mounted on a SMPS board cooled under mixed convection. (September 2018)

• Record Type: Journal Article
• Authors: Mathew, V.K.; Hotta, Tapano Kumar
• Is Part Of: Thermal science and engineering progress. Volume 7(2018)
• Page Start: 221
• Page End: 229
• Publication Date: 2018-09
• Subjects: ANSYS Icepack -- Artificial neural network -- Genetic algorithm -- IC chips -- Mixed convection -- Optimal configuration; Heat engineering -- Periodicals; Heat engineering; Thermodynamics; Periodicals; 621.402
• DOI: 10.1016/j.tsep.2018.06.010
• Languages: English
• ISSNs: 2451-9049

Abstract

Highlights: Heat transfer from seven non-identical IC chips mounted on a SMPS board under mixedconvection. Optimal arrangement of these heat sources using hybrid optimization strategy. Use of numerical data driven ANN-GA technique to predict the optimal distribution. Temperature of heat sources is a strong function of their size, position on the substrate board. Comparison of the optimal arrangement obtained from ANN-GA technique with conventional methods. Abstract: The paper aims to investigate numerically the mixed convection heat transfer characteristics from seven non-identical IC chips (Aluminium) mounted on a Switch Mode Power Supply (SMPS) board (substrate) made by FR-4 (glass-reinforced epoxy laminate material). The objective is to determine the optimum configuration of these IC chips positioned at different locations on the substrate board. The optimum configuration is proposed by defining a non-dimensional geometric distance parameter ( λ ) and by employing a hybrid strategy (collaborating Artificial neural network (ANN) and Genetic algorithm (GA)). 3D, steady state numerical simulations are carried out using ANSYS Icepak to determine the temperature distribution of the IC chips. It has been confirmed that, the temperature of the IC chips strongly rely on their shape, size, and location on the substrate board. The hybrid optimization is the most robust technique to predict the arrangement of the IC chips on the substrate board more accurately, as compared to conventional methods.