Vertical InGaAs tunnel-field-effect transistors by an electro-plating fin formation technique. (February 2020)

• Record Type: Journal Article
• Authors: Baek, Ji-Min; Jo, Hyeon-Bhin; Yun, Do-Young; Lee, In-Geun; Lee, Changmin; Shin, Chan-Soo; Kim, Hyoungsub; Ko, Dae-Hong; Kim, Tae-Woo; Kim, Dae-Hyun
• Is Part Of: Solid-state electronics. Volume 164(2020)
• Publication Date: 2020-02
• Subjects: Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2019.107681
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: In this letter, we introduce for the first time a nano-fin patterning technique that combines Au electro-plating and high-temperature InGaAs dry etching processes. We applied this technique to fabricate vertical homojunction InGaAs tunnel-field-effect-transistors (TFETs). An InGaAs fin width (Wfin ) of 60 nm was implemented with excellent line-edge-roughness (LER). The fabricated vertical homojunction InGaAs TFETs with a gate length (Lg ) of 100 nm exhibited excellent device characteristics, such as a minimum subthreshold swing (Smin ) of 80 mV/decade, an on–off-ratio (ION /IOFF ) of 6.09 × 10 2 at VDS = 0.3 V, and a drain induced barrier lowering (DIBL) of 208 mV/V at room temperature.