Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode. (9th September 2019)

• Record Type: Journal Article
• Authors: Kim, Hyeonjeong; Kang, In Man; Cho, Seongjae; Sun, Wookyung; Shin, Hyungsoon
• Is Part Of: Semiconductor science and technology. Volume 34:Number 10(2019)
• Publication Date: 2019-09-09
• Subjects: capacitorless DRAM -- grain boundary -- poly-Si 1T-DRAM -- junctionless (JL) transistor; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/ab3a07
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: Capacitorless DRAM (1T-DRAM) is considered to be a promising candidate to replace conventional 1T-1C DRAM which is facing a scaling limit. 1T-DRAM with a poly-Si body has attracted much attention specifically for its simple SOI fabrication and stackable memory which allow for ultrahigh density. A single crystal silicon-based junctionless (JL) transistor is unsuitable for a 1T-DRAM cell because the transistor's body is too thin to have a storage region and its junction barrier is too low to store holes. In contrast, a JL transistor with a thin poly-Si body can be used as a 1T-DRAM cell because it uses a grain boundary as its charge storage region instead of a floating body. We carried out intensive simulations of JL transistors with poly-Si body and confirmed the possibility of using a JL structure as a poly-Si 1T-DRAM cell. In addition, we analyzed the memory mechanism and characteristics of this structure.