A framework for high-level simulation and optimization of fine-grained reconfigurable architectures. (August 2019)

• Record Type: Journal Article
• Authors: Pasha, Muhammad Adeel; Farooq, Umer; Siddiqui, Bilal
• Is Part Of: Simulation. Volume 95:Number 8(2019)
• Page Start: 737
• Page End: 751
• Publication Date: 2019-08
• Subjects: High-level simulation -- embedded systems -- reconfigurable architectures -- Field Programmable Gate Array; Computer simulation -- Periodicals; 003.3
• DOI: 10.1177/0037549718796272
• Languages: English
• ISSNs: 0037-5497

Abstract

Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a fine-grained reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This article proposes an automated design-flow for the system-level simulation, optimization, and resource estimation of generic as well as custom fine-grained reconfigurable architectures. The proposed framework is generic in nature as it can be used for both control-oriented and compute-intensive applications and then generates a homogeneous or heterogeneous reconfigurable architecture for them. Four sets of homogeneous and heterogeneous benchmarks are used in this work to show the efficacy of our proposed design-flow, and simulation results reveal that our framework can generate both generic and custom fine-grained reconfigurable architectures. Moreover, the area and power estimations show that auto-generated domain-specific reconfigurable architectures are 76% and 73% more area and power-efficient, respectively, than generic FPGA-based implementations. These results are consistent with the savings reported for manual designs in the literature.