Exploring the applicability of well optimized dielectric pocket tunnel transistor for future low power applications. (February 2019)

• Record Type: Journal Article
• Authors: Upasana, ; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula
• Is Part Of: Superlattices and microstructures. Volume 126(2019)
• Page Start: 8
• Page End: 16
• Publication Date: 2019-02
• Subjects: Ambipolar devices -- Asymmetric drain -- Dielectric pocket -- Dual material gate TFET -- Dual material gate hetero-dielectric TFET -- Energy efficient devices -- Hetero-dielectric TFET -- TFET -- Tunnel transistors; Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2018.12.005
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: This work is an extension of our previous work where the major focus was to understand the device physics and optimize its performance. In this extended work, we intend to investigate the applicability of Dielectric pocket (DP) based TFETs for low power applications. For that, firstly the device architecture is well optimized by imposing several gate and dielectric engineering techniques and thereafter the well optimized architecture is verified for analog, digital and wireless applications. Different TFET based device architectures have been examined using ATLAS simulation software. The key points citing each of the device architectures i.e. DP Hetero-Dielectric (H-D) TFET, DP Dual Material Gate (DMG) TFET and DP Dual Material Gate Hetero-Dielectric (DMG H-D) TFET with their merits and limitations for the future applications have been explained. During the analysis, it was found that DP H-D TFET outperforms other two cases and hence it has been further examined for analog applications using gm1 /Ids (transconductance versus drain current) factor. For low power oriented digital applications, parasitic capacitances and inverter circuit with resistive load was analyzed. Further, for wireless applications device linearity and distortion governing parameters have been analyzed. It was concluded that DP H-D TFETs are highly applicable to be used for upcoming energy efficient applications. Highlights: DP TFET architecture is well optimized by imposing several gate and dielectric engineering techniques. The merits and limitations of DP H-D TFET, DP DMG TFET and DP DMG H-D TFET for the future applications have been explained. For low power oriented digital applications, parasitic capacitances and inverter circuit with resistive load was analyzed. For wireless applications device linearity and distortion governing parameters have been analyzed. DP H-D TFETs are highly applicable to be used for upcoming energy efficient applications.