Extrinsic gate capacitance compact model for UTBB MOSFETs. (30th November 2017)

• Record Type: Journal Article
• Authors: Martinez-Lopez, Andrea G; Tinoco, Julio C; Lezama, Gamaliel; Conde, Jorge E; Esfeh, Babak Kazemi; Raskin, Jean-Pierre
• Is Part Of: Semiconductor science and technology. Volume 33:Number 1(2018:Jan.)
• Publication Date: 2017-11-30
• Subjects: UTBB -- parasitic gate capacitance -- modeling -- cut-off frequency; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/aa98e7
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: Ultra-thin body and buried oxide transistors have gained attention as candidates for near future CMOS technology nodes. Recent studies have pointed out that the total parasitic gate capacitance becomes an important concern for very-high frequency performance. In this paper a semi-analytical model to describe the total extrinsic gate capacitance for ultrathin silicon body and buried oxide transistors is presented. The developed model considers the main technological parameters and has been verified by finite-element numerical simulations as well as by comparison with experimental measurements. The relative weight of the main parasitic components is addressed as well as their impact over the current gain cut-off frequency. Finally, the possibility to improve the cut-off frequency by about 35% due to the reduction of the parasitic gate capacitance is highlighted.