Analytical model of surface potential and threshold voltage in gate-drain overlap FinFET. (May 2018)

• Record Type: Journal Article
• Authors: Das, Rajashree; Baishya, Srimanta
• Is Part Of: Microelectronics journal. Volume 75(2018)
• Page Start: 153
• Page End: 159
• Publication Date: 2018-05
• Subjects: FinFET -- Surface potential -- Threshold voltage -- Overlap; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.04.005
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A gate-drain overlapped FinFET, which provides low leakage current (I OFF ), high I ON current, and high I ON / I OFF ratio with low subthreshold swing ( SS ), is proposed. To have better physical inside of the proposed structure, a 3-D analytical model of surface potential is derived by solving Poisson's equation in the channel and overlap regions using superposition principle. Using the surface potential, a closed form expression for the threshold voltage is also derived. Both the surface potential and threshold voltage models show good agreement with TCAD simulation data for different values of channel lengths, fin heights, fin widths, gate work functions, and channel concentrations. Furthermore, the performance of the device is evaluated in digital circuit applications and interestingly, no overshoot and undershoot are observed in the transient characteristics in case of a low power inverter. Investigation shows that the gate-drain overlap region influences the device characteristics significantly. Highlights: The proposed FinFET provides good electrostatic integrity as less IOFF, high ION, high ION /IOFF, and less SS. 3-D analytical model of surface potential for the channel as well as for overlap region is derived. Without using any fitting parameter and numerical technique, a closed form expression of Vth is developed. The proposed device efficiency is evaluated in digital inverter circuit.