Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability. (February 2018)

• Record Type: Journal Article
• Authors: Mukhopadhyay, Subhadeep; Lee, Yung-Huei; Lee, Jen-Hao
• Is Part Of: Microelectronics and reliability. Volume 81(2018)
• Page Start: 226
• Page End: 231
• Publication Date: 2018-02
• Subjects: Planar -- SoC -- FinFET -- BTI -- SRAM -- SNM -- Vmin; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.12.044
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In this study a careful analysis of the device and the circuit level variability and reliability are presented. Planar 20 nm System on Chip (SoC), 16 nm FinFET (16FF) and 10 nm FinFET (10FF) devices are studied to understand the time-zero process variability and Bias Temperature Instability (BTI) stress induced (time dependent) threshold voltage (VT ) variations to evaluate the device degradation. Moreover, to understand the circuit level variability, the 6-Transistor (6T) SRAM performance is assessed in terms of the static noise margin (SNM) degradation under the influence of BTI stress. Finally, the product level SRAM performance is studied in terms of the minimum SRAM operating voltage (Vmin) degradation. Highlights: This work presents the device & circuit variability and BTI reliability for advanced FinFET devices. The circuit level SRAM performances are studied at time zero and also under the influence of BTI stress. The product level SRAM performances are studied in terms of the minimum SRAM operating voltage (Vmin) degradation.