Fast identification of true critical paths in sequential circuits. (February 2018)

• Record Type: Journal Article
• Authors: Ubar, Raimund; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Jürimägi, Lembit
• Is Part Of: Microelectronics and reliability. Volume 81(2018)
• Page Start: 252
• Page End: 261
• Publication Date: 2018-02
• Subjects: Timing-critical path -- Gate-level analysis -- NBTI; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.11.027
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a fast simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like selecting the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The high scalability of the method is achieved by using a novel fast method for finding activated paths for many test patterns in parallel, a novel algorithm to determine only a small subset of critical paths, and a novel method for identifying the true critical paths among this subset, using branch and bound strategy. The paper demonstrates efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique. Highlights: A fast simulation-based technique for identification of true timing-critical paths in combinational and sequential circuits. Application for gate-level reliability analysis tasks. The practically infeasible exploration of true critical paths in sequential circuits is transformed to a scalable task. The search space is constrained by the set of feasible state transitions in the sequential circuit. The complexity is reduced by using static bounds and by using dedicated branch-and-bound search strategy.