Source/drain eSiGe engineering for FinFET technology. (17th August 2017)

• Record Type: Journal Article
• Authors: Peng, Jianwei; Qi, Yi; Lo, Hsien-Ching; Zhao, Pei; Yong, Chloe; Yan, Jianghu; Dou, Xinyuan; Zhan, Hui; Shen, Yanping; Regonda, Suresh; Hu, Owen; Yu, Hong; Joshi, Manoj; Adams, Charlotte; Carter, Rick; Samavedam, Srikanth
• Is Part Of: Semiconductor science and technology. Volume 32:Number 9(2017:Sep.)
• Publication Date: 2017-08-17
• Subjects: Fin-sidewall-spacer -- FinFET -- eSiGe -- epitaxy -- diamond -- saturation; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/aa7d3f
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: Epitaxy growth loading effect—the growth rate difference between device macros due to their local open ratio difference—is an important consideration for device design and thus process optimization. A poor loading process leads to device performance delta across macros. For eSiGe on FinFETs, we found that optimized eSiGe on FinFETs saturates as the eSiGe diamond pins at fin top surface and the fin-sidewall-spacer (FSS). The eSiGe diamond size measured by lateral CD does not increase with deposition time, but it linearly correlates to cavity depth and FSS pushdown. In principle, the eSiGe loading effect can be addressed with an extended growth time until every device macros saturates. However, it is found that, the epitaxy growth related defects, measured by abnormal eSiGe and unwanted growth, can also be elevated to an unacceptable level for a longer deposition time. Thus, the eSiGe loading process still needs to be optimized for an improved process window. In this work, an optimized eSiGe process achieves reduced loading between 2-fin and 40-fin macros and thus a smaller pFET performance gap between the two device macros.