BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics. (March 2016)

• Record Type: Journal Article
• Authors: Jain, Sonal; Gupta, Deepika; Neema, Vaibhav; Vishwakarma, Santosh
• Is Part Of: Journal of semiconductors. Volume 37:Number 3(2016:Mar.)
• Publication Date: 2016-03
• Subjects: 85.25.Hv -- 85.30.−z -- 2520; high-k dielectric materials -- nonvolatile memory -- tunnel barrier -- retention -- endurance and bandgap-engineered; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1674-4926/37/3/034002
• Languages: English
• ISSNs: 1674-4926

Abstract

Abstract: We investigate the effect of a high- k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO3 /HfAlO/SiO2 . These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS). In the proposed structure HfAlO and AlLaO3 replace Si3 N4 and the top SiO2 layer in a conventional oxide/nitride/oxide (ONO) tunnel stack. Due to the lower conduction band offset (CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase (P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high- k materials while scaling, for the same equivalent oxide thickness (EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4% (at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.