Analytical gate fringe capacitance model for nanoscale MOSFET with layout dependent effect and process variations. (19th June 2018)

• Record Type: Journal Article
• Authors: Sun, Yabin; Liu, Ziyu; Li, Xiaojin; Ren, Jiaqi; Zheng, Fanglin; Shi, Yanling
• Is Part Of: Journal of physics. Volume 51:Number 27(2018)
• Publication Date: 2018-06-19
• Subjects: MOSFET -- fringing capacitance -- process variation -- layout-dependent effect; Physics -- Periodicals; 530
• DOI: 10.1088/1361-6463/aac7d0
• Languages: English
• ISSNs: 0022-3727

Abstract

Abstract: In this paper, we present an analytical closed model for the gate to source/drain fringing capacitance ( C f ) of nanoscale metal oxide semiconductor field effect transistors (MOSFETs), with the consideration of layout dependent effects and process fluctuations. A kind of field-poly structure on shallow trench isolation (STI) is used to separate C f from other gate-around parasitic capacitances. A significant layout-dependent-effect is found in C f for the case with high contact density. Based on the device structure, C f is divided and analytically modeled by three dual- k perpendicular-plate capacitances. The effects of gate to contact space (CPS), contact to contact space (CCS) and the process variations, such as the over-etching of source/drain contact, are taken into account. The proposed model is validated on 40 nm MOSFETs, with a series of layout parameters, and good agreement is obtained between the modeled and measured data over a large range of CPS and CCS. The proposed model can improve the precision for digital and RF circuit simulation in sub-nanometer technology generation.