Achievement of low parasitic resistance in Ge n-channel metal-oxide-semiconductor field-effect transistor using an embedded TiN-source/drain structure. (24th January 2017)

• Record Type: Journal Article
• Authors: Nagatomi, Y; Tateyama, T; Tanaka, S; Yamamoto, K; Wang, D; Nakashima, H
• Is Part Of: Semiconductor science and technology. Volume 32:Number 3(2017:Mar.)
• Publication Date: 2017-01-24
• Subjects: Ge -- parasitic resistance -- metal S/D -- n-MOSFET; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/1361-6641/32/3/035001
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: We investigated the source/drain (S/D) parasitic resistance ( R P ) of a Ge n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) with TiN-S/D. The R P was as high as ∼1400 Ω, which is attributed to a very thin amorphous interlayer ( a -IL) at a TiN/Ge interface. To solve this problem, n-MOSFETs with an embedded S/D structure were fabricated, of which the S/D was formed by the etching of a Ge layer using 0.03%-H2 O2 solution followed by TiN sputter deposition. The electrical performances were investigated for devices with etching depths in the range of 2–22 nm. The devices with etching depths of 2–5 nm did not work. The devices with etching depths of 12–15 nm showed a quite normal transistor operation, and the R P was as low as ∼130 Ω, which is comparable to that of a p-MOSFET with PtGe-S/D. However, R P s of the devices with etching depths of ∼22 nm was considerably high. The reason for these results is discussed on the basis of an a -IL formation at the sidewall of the engraved S/D region.