Impact of sidewall etching on the dynamic performance of GaN-on-Si E-mode transistors. (September 2018)

• Record Type: Journal Article
• Authors: Tajalli, A.; Canato, E.; Nardo, A.; Meneghini, M.; Stockman, A.; Moens, P.; Zanoni, E.; Meneghesso, G.
• Is Part Of: Microelectronics and reliability. Volume 88/90(2018)
• Page Start: 572
• Page End: 576
• Publication Date: 2018-09
• Subjects: GaN -- High-electron-mobility transistor -- p-GaN gate -- Threshold voltage shift -- Trapping mechanism; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.06.037
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The aim of this paper is to investigate the role of the etching of the sidewalls of p-GaN on the dynamic performance of normally-off GaN HEMTs with p-type gate. We analyze two wafers having identical epitaxy but with different recipes for the sidewall etching, referred to as "Etch A" (non-optimized) and "Etch B" (optimized). We demonstrate the following relevant results: (i) the devices with non-optimized etching (Etch A), when submitted to positive gate bias, show a negative threshold voltage shift and a decrease in Ron, which are ascribed to hole injection under the gate and/or in the access regions; (ii) transient characterization indicates the existence of two trap states, with activation energies of 0.84 eV (CN defects) and 0.30 eV. The latter (with time-constants in the ms range) is indicative of the hole de-trapping process, possibly related to trap states in the AlGaN barrier or at the passivation/AlGaN interface; (iii) by optimizing the p-GaN sidewall etching (for the same epitaxy) it is possible to completely eliminate the threshold voltage shift. This indicates that hole injection mostly takes place along the sidewalls. Highlights: Role of the etching of the sidewalls of p-GaN on the p-GaN HEMTs performance Forward gate stress: ID increase, VTH instability, RON decrease Two trapping mechanisms: carbon impurities and hole de-trapping Suppression negative threshold voltage shift by the p-GaN sidewall etching Hole trapping mostly takes place on the sidewalls.