Ferroelectric properties of SOS and SOI pseudo-MOSFETs with HfO2 interlayers. (September 2019)

• Record Type: Journal Article
• Authors: Popov, V.P.; Antonov, V.A.; Ilnitsky, M.A.; Tyschenko, I.E.; Vdovin, V.I.; Miakonkikh, A.V.; Rudenko, K.V.
• Is Part Of: Solid-state electronics. Volume 159(2019)
• Page Start: 63
• Page End: 70
• Publication Date: 2019-09
• Subjects: Silicon-on-sapphire pseudo-MOSFETs -- Hafnium oxide interlayer -- Ferroelectric phase -- Polarization mechanism; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2019.03.036
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: SOI and SOS pseudo-MOSFETs with 20 nm hafnia interlayers show normal gate-drain characteristics after annealing ≥ 1000 °C with the carrier mobility as in bulk silicon. Highly stable ferroelectric hysteresis was observed in the case of SOS pseudo-MOSFETs. Formation of a HfO2 film, having the ferroelectric phase OII ( Pmn21 ) is stabilized by a compressive stress in the case of SOS pseudo-MOSFETs. Abstract: The formation of a multi-crystalline HfO2 film, containing the ferroelectric phase OII ( Pmn21 ) after a high-temperature annealing at 1100 °C, was experimentally observed by HREM for the first time in silicon-on-sapphire (SOS) structures obtained by direct bonding and a hydrogen transfer of silicon layer on Si or C-sapphire substrates, respectively. PEALD HfO2 interlayers with the thickness of 20 nm were deposited on silicon before bonding to reduce the defects and magnitude of their charge at the SOS and silicon-on-insulator (SOI) interfaces. SOS pseudo-MOS transistors demonstrate standard drain-gate characteristics with the same charge carrier mobility as in bulk silicon and a small positive fixed charge (≤1.2 × 10 12 cm −2 ). Moreover, a stable ferroelectric hysteresis with ΔVG ∼700 V observed only in SOS FETs is promising for the embedded memory formation and it extends the functionality of logic circuits. It was concluded that the OII phase is stabilized mainly by a high compressive stress and it can be responsible for the hysteresis in the case of SOS pseudo-MOSFETs opposite to the SOI-structure.