Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures. (September 2019)

• Record Type: Journal Article
• Authors: Beckers, Arnout; Jazaeri, Farzan; Bohuslavskyi, Heorhii; Hutin, Louis; De Franceschi, Silvano; Enz, Christian
• Is Part Of: Solid-state electronics. Volume 159(2019)
• Page Start: 106
• Page End: 115
• Publication Date: 2019-09
• Subjects: 28 nm FDSOI -- Characterization -- Cryogenic CMOS -- Cryogenic MOSFET -- Double-gate -- Low temperature -- Mobility -- Modeling -- 4.2 K; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2019.03.033
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long p MOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.