Impact and mitigation of SRAM read path aging. (August 2018)

• Record Type: Journal Article
• Authors: Agbo, Innocent; Taouil, Mottaqiallah; Kraak, Daniël; Hamdioui, Said; Weckx, Pieter; Cosemans, Stefan; Catthoor, Francky; Dehaene, Wim
• Is Part Of: Microelectronics and reliability. Volume 87(2018)
• Page Start: 158
• Page End: 167
• Publication Date: 2018-08
• Subjects: Bit-line swing -- SD -- BTI -- SRAM sense amplifier; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.05.011
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technology nodes, and inspects both the bit-line swing ( BLS ) (which reflect the degradation of the cell) and the sensing delay ( SD ) (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the SD degradation strongly depends on the workload, supply voltage, temperature, and technology nodes (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation (up to 15.2% improvement) is more effective for the SRAM read path than cell mitigation (up to 11.4% improvement). Highlights: We have added the analysis of time-dependent variations as a cause of aging and degradation. For this analysis, we experimented with different supply voltages (i.e., from -10% Vdd to +10% Vdd), different temperatures (i.e., 233K, 298K, and 348K), and different workloads. We have added analysis for different technology nodes (i.e., 45-, 32-, and 22-nm). Where we experimented with different workloads, nominal supply voltage per technology nodes, and at a nominal temperature. We have added mitigation technique to mitigate the impact of aging and extend the lifetime of design. The technique is analyzed and the obtained results are compared with the initial design in order to validate the scheme. The evaluation has been done for different workload and by considering three important metrics (i.e., Bit line swing, sensing delay, and energy). We have added cell stability in the presence of the mitigation scheme (for both time zero and time-dependent variations) in order to explore the potential impact on the memory robustness. The results are compared with those of initial design. We have considered three metrics (i.e., HSNM, RSNM, and WTP) for this analysis. We have added an extensive section to discuss the main obtained results and extract the main messages and conclusions.