Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure. (23rd October 2017)

• Record Type: Journal Article
• Authors: Yang, X.; Wu, N.; Andrian, J. H.
• Other Names: Li Xueqing Academic Editor.
• Is Part Of: VLSI design. Volume 2017(2017)
• Publication Date: 2017-10-23
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/2017/4914301
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96% total power reduction compared with the original MBUS implementation.