Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. Issue 3 (2002)

• Record Type: Journal Article
• Authors: Lee, Yu-Min; Chen, Charlie Chung-Ping; Chang, Yao-Wen; Wong, D. F.
• Is Part Of: VLSI design. Volume 15:Issue 3(2002)
• Page Start: 587
• Page End: 594
• Publication Date: 2002
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1080/1065514021000012200
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : Delay, power, skew, area and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.