IDDQ Detectable Bridges in Combinational CMOS Circuits. Issue 3 (1997)

• Record Type: Journal Article
• Authors: Isern, E.; Figueras, J.
• Is Part Of: VLSI design. Volume 5:Issue 3(1997)
• Page Start: 241
• Page End: 252
• Publication Date: 1997
• Subjects: Bridging faults -- current testing -- functional redundancy -- functional equivalence -- functional redundancy removal; Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/1997/93809
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : Undetectable stuck-at faults in combinational circuits are related to the existence of logic redundancy ( s-redundancy ). Similarly, logically equivalent nodes may cause some bridging faults to become undetectable byI D D Q testing. An efficient method for the identification and removal of such functionally equivalent nodes ( f-redundant nodes ) in combinational circuits is presented. OBDD graphs are used to identify the functional equivalence of candidate to f-redundancy nodes. An f-redundancy removal algorithm based on circuit transformations to improve bridging fault testability, is also proposed. The efficiency of the identification and removal of f-redundancy has been evaluated on a set of benchmark circuits.