A Parallel Residue-to-binary Converter for the Moduli Set {2m−1, 220m+1, 221m+1, …, 22km+1}. Issue 2 (2002)

• Record Type: Journal Article
• Authors: Wang, Wei; Swamy, M. N. S.; Ahmad, M. O.; Wang, Yuke
• Is Part Of: VLSI design. Volume 14:Issue 2(2002)
• Page Start: 183
• Page End: 191
• Publication Date: 2002
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1080/10655140290010097
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : In this paper, a high-speed parallel residue-to-binary converter is proposed for a recently introduced moduli setS k = { 2 m − 1, 2 2 0 m + 1, 2 2 1 m + 1, …, 2 2 k m + 1 } for a general value ofk . The proposed converter uses simple cyclic shift and concatenation operations and does not require any multiplier. Individual converters for the cases ofk = 0 andk = 1 are derived from the general architecture and compared with those existing in the literature. The converter forS 0 is twice as fast requiring only one-half of the hardware, while that ofS 1 is three times as fast, but requiring only 60% of the hardware, as compared to the corresponding ones existing in the literature. Furthermore, the proposed converters are implemented using 0.5-micron CMOS VLSI technology. Based onS 0, the layouts for 8-bit, 16-bit, 32-bit and 64-bit converters are generated, and the corresponding simulation results obtained.