Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits. (8th June 2016)

• Record Type: Journal Article
• Authors: Saini, Vikas K.; Akhter, Shamim; Chauhan, Tanuj
• Other Names: Lee Chang-Ho Academic Editor.
• Is Part Of: VLSI design. Volume 2016(2016)
• Publication Date: 2016-06-08
• Subjects: Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/2016/1260879
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX.