An Efficient Parallel VLSI Sorting Architecture. Issue 2 (2000)

• Record Type: Journal Article
• Authors: Zhang, Yanjun; Zheng, S. Q.
• Is Part Of: VLSI design. Volume 11:Issue 2(2000)
• Page Start: 137
• Page End: 147
• Publication Date: 2000
• Subjects: Sorting network -- VLSI -- special-purpose architecture -- systolic array -- circuit layout; Integrated circuits -- Very large scale integration -- Periodicals; 621.395
• DOI: 10.1155/2000/14617
• Languages: English
• ISSNs: 1065-514X

Abstract

Abstract : We present a new parallel sorting algorithm that uses a fixed-size sorter iteratively to sort inputs of arbitrary size. A parallel sorting architecture based on this algorithm is proposed. This architecture consists of three components, linear arrays that support constant-time operations, a multilevel sorting network, and a termination detection tree, all operating concurrently in systolic processing fashion. The structure of this sorting architecture is simple and regular, highly suitable for VLSI realization. Theoretical analysis and experimental data indicate that the performance of this architecture is likely to be excellent in practice.