Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. Issue 9 (August 2015)

• Record Type: Journal Article
• Authors: Gomes, Iuri A.C.; Martins, Mayler G.A.; Reis, André I.; Kastensmidt, Fernanda Lima
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 9/10(2015)
• Page Start: 2072
• Page End: 2076
• Publication Date: 2015-08
• Subjects: Triple Modular Redundancy (TMR) -- Approximate circuit -- Approximate-TMR -- Fault tolerance -- Transient faults; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.06.125
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The use of Triple Modular Redundancy (TMR) with majority voters can guarantee 100% single fault masking coverage for a given circuit against transient faults. However, this methodology presents a minimum area overhead of 200% compared to the original circuit. In order to reduce considerably the area overhead without compromising significantly the fault coverage, TMR can use approximated logic circuits to generate redundant modules that are optimized for area, compared to the original module. In this work, we propose the use of only approximate logic modules to compose the TMR in order to reduce the area overhead close to minimal values. We use a Boolean factorization based method to compute approximate functions and to select the best composition of approximate logic. The circuits are mapped using the ABC logic synthesis tool and an academic cell library. All the tests are performed using a fault injection tool designed specifically to cope with logic gate and transistor description level. For a combinational circuit (5 inputs, 10 literals) the results have shown that it is possible to maintain the maximum protected p–n junction ratio of 98.88% with only 165% area overhead when using ATMR; and a maximum of 94.66% protected p–n junction ratio with only an 88% area when using full-ATMR. Results for a 4-bit ripple-carry adder showed a protected p–n juncion ratio of almost 97% with 168% area overhead and 93.5% with only 136% area overhead. Highlights: To reduce the area of TMR it is possible to use approximate redundant modules. Two case-studies, a simple function (5 inputs/10 literals) and a 4-bit adder ATMR can provide a good balance between area overhead and fault coverage. For the 4-bit adder the best way to achieve a good balance is to use ATMR by level.