Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology. (September 2015)

• Record Type: Journal Article
• Authors: Sun, Lijie; Shang, Ganbing; Liu, Linlin; Cheng, Jia; Guo, Ao; Ren, Zheng; Hu, Shaojian; Chen, Shoumian; Zhao, Yuhang; Chan, Mansun; Zhang, Long; Li, Xiaojin; Shi, Yanling
• Is Part Of: Solid-state electronics. Volume 111(2015)
• Page Start: 118
• Page End: 122
• Publication Date: 2015-09
• Subjects: Gate-to-source/drain fringing capacitance -- Gate-to-contact capacitance -- Layout-dependent -- SPICE model -- Contact to poly space -- Contact to contact space; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.05.033
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: A novel test key is designed to separate gate-to-source/drain fringing capacitance ( C f ) and gate to contact capacitance ( C co ). Layout-dependence is modeling in C f based on silicon data using 40 nm CMOS technology. Modeling equations are precise and efficient. Layout-dependent C f model are more accurate to silicon in circuit simulation. Abstract: In this paper, MOSFET layout-dependent gate-around capacitance which include gate-to-source/drain fringing capacitance ( C f ) separated from gate-to-contact capacitance ( C co ), has been extracted in SPICE model. This work focuses on layout-dependent-effect (LDE) in AC characteristics such as C f and C co of MOSFET. To separate C f and C co, novel test structures have been designed and fabricated by 40 nm process. According to the silicon data, the apparent variation of C f with contact to poly space (CPS) and contact to contact space (CCS) has been modeled and exactly extracted. The errors between silicon data and simulation are mainly under 5%. The extraction and modeling of the layout-dependent C f in this work will contribute high accuracy for digital and RF circuit simulation in advanced CMOS node.