Determination of DC equivalent hot carrier stress times in scaled CMOS devices using novel AC stress methodology. (February 2019)

• Record Type: Journal Article
• Authors: Kerber, Andreas; Nigam, Tanya
• Is Part Of: Microelectronics and reliability. Volume 93(2019)
• Page Start: 98
• Page End: 101
• Publication Date: 2019-02
• Subjects: Bias temperature instability -- Metal gate -- High-k dielectrics -- CMOS devices; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.12.012
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: A new AC hot carrier injection (HCI) test methodology replicating the switching in digital CMOS circuits is introduced to correlate HCI in discrete scaled CMOS devices to HCI in logic circuits. This technique allows us to demonstrate that the historic 50× reduction for definition of DC HCI lifetime targets for mid-Vg stress in scaled devices should be uplifted to 1000× based on the correlation with RO degradation for poly-Si/SiON and 14 nm FinFET data. This brings significant HCI relief for device optimization in scaled technology nodes. Highlights: A new AC Hot Carrier Injection (HCI) test methodology replicating the switching in digital CMOS circuits is introduced. The AC HCI methodology is used to correlate HCI in discrete scaled CMOS devices to HCI in logic circuits. This technique allows to modulate the HCI contribution by adjusting the gate and drain waveform offset. Based on RO degradation data of scaled technology nodes a more progressive DC HCI lifetime target definition is recommended. This brings significant HCI relief for device optimization in scaled technology nodes.