Characteristics and reliability of VDMOS under capacitive loads. (February 2019)

• Record Type: Journal Article
• Authors: Zhang, Yulong; Wang, Lulu; Gong, Xueqin; Gao, Bo; Wang, Lixin; Luo, Jiajun
• Is Part Of: Microelectronics and reliability. Volume 93(2019)
• Page Start: 8
• Page End: 15
• Publication Date: 2019-02
• Subjects: VDMOS -- Capacitive loads -- Failure mechanism -- Thermal characteristics -- Structure -- Process; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.12.008
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The failure mechanism of vertical double-diffusion metal-oxide-semiconductor (VDMOS) turning on under capacitive loads is analyzed. Due to the structural features of the device, it is easy to burnout at the source pad (SPAD) area when turning on under capacitive loads. On the basis of simulation, thermal characteristics of VDMOS devices under capacitive loads are analyzed. The results show that junction temperatures ( T j ) are obviously affected by capacitive load values ( C L ) and thermal resistances ( R th ) of VDMOS devices. When R th = 0.1 °C/W or R th = 0.15 °C/W, curves between T j and C L present an approximately linear relationship, while when R th = 0.2 °C/W, the rate of T j rising with C L shows an increasing trend. At last, the influences of device structure and process on capacitive load limits are verified by experiments. The results show that the design of local oxidation of silicon (LOCOS) structure has little effect on capacitive load limits of devices, while the capacitive load limit of the fourth generation (R4) process devices is obviously higher than that of the fifth generation (R5) process devices. Highlights: The junction temperature is obviously affected by capacitive loads and thermal resistances of devices. The design of LOCOS structure has little effect on capacitive load limits of devices. The capacitive load limits of R4 process devices is obviously higher than that of R5 process devices.