A BICS-based strategy for mitigating the effects of single event transients on SAR converter. (February 2019)

• Record Type: Journal Article
• Authors: Gao, Jing; Ding, Yingguang; Nie, Kaiming; Xu, Jiangtao
• Is Part Of: Microelectronics and reliability. Volume 93(2019)
• Page Start: 45
• Page End: 56
• Publication Date: 2019-02
• Subjects: Analog-To-Digital Converter -- Single event transients -- Radiation environment -- BICS; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.12.013
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: This paper presents a new strategy to mitigate the effects of single event transients (SETs) on the analog part of the Successive Approximation Register (SAR) Analog-To-Digital Converter (ADC). According to the mechanism of error, a series of bulk built-in current sensors (BICS) and D Flip-Flops constitutes a feedback control circuit, which is used to distinguish a negative effect of SETs on SAR ADC and produce related control signal. By sampling backup signal and canceling offset voltage of comparator, the imbalanced charge of capacitor array and storage capacitor of comparator due to a particle strike can be restored respectively. Meanwhile, SAR logic will repeat the comparison of the current step instead of reading the erroneous comparison result by shielding the edge of current clock signal. On the basis of this method, the fault is not propagated to the remaining conversions, thus substantially reducing the conversion error magnitude. In addition, this BICS-based technique can be combined with conventional radiation-hardened methods to achieve higher reliability. Finally, the circuit level fault injection simulation results demonstrate that this proposed method significantly mitigates influence of SETs on the analog part of the SAR ADC in 130 nm CMOS process.