Deep insight into DC, RF/analog, and digital inverter performance due to variation in straggle parameter for gate modulated TFET. (1st March 2019)

• Record Type: Journal Article
• Authors: Saha, Rajesh; Vanlalawmpuia, K.; Bhowmick, Brinda; Baishya, Srimanta
• Is Part Of: Materials science in semiconductor processing. Volume 91(2019)
• Page Start: 102
• Page End: 107
• Publication Date: 2019-03-01
• Subjects: DC characteristic -- Digital inverter -- RF/analog parameter -- Straggle parameter; Semiconductors -- Periodicals; Integrated circuits -- Materials -- Periodicals; Semiconducteurs -- Périodiques; Circuits intégrés -- Matériaux -- Périodiques; Electronic journals; 621.38152
• DOI: 10.1016/j.mssp.2018.11.011
• Languages: English
• ISSNs: 1369-8001

Abstract

Abstract: A systematic investigation on the effect of variation in lateral straggle for a gate-modulated Tunnel FET (GM-TFET) performance is investigated. At the time of ion implantation, a nonzero tilt angle extents the dopant of source/drain regions into the channel, which in turn, reduces the channel length resulting in degradation of device performance. This work highlighted the DC performances like transfer characteristic, output characteristic, subthreshold swing (SS), and Ion /Ioff ratio due to variation in the lateral straggle parameter (σ) from 0 to 6 nm. Further, the impact of σ on analog/RF figure of merits (FOMs) such as transconductance (gm ), output conductance (gd ), intrinsic gain (gm /gd ), total gate capacitance (Cgg ), and cut-off frequency (ft ) are also investigated. Finally, the performance of digital inverter in GM-TFET for different σ was carried out. The study was based on TCAD simulations.