Improvement in drain-induced-barrier-lowering and on-state current characteristics of bulk Si fin field-effect-transistors using high temperature Phosphorus extension ion implantation. (February 2019)

• Record Type: Journal Article
• Authors: Kikuchi, Yoshiaki; Hopf, Toby; Mannaert, Geert; Everaert, Jean-Luc; Kubicek, Stefan; Eyben, Pierre; Waite, Andrew; del Agua Borniquel, Jose Ignacio; Variam, Naushad; Mocuta, Dan; Horiguchi, Naoto
• Is Part Of: Solid-state electronics. Volume 152(2019)
• Page Start: 58
• Page End: 64
• Publication Date: 2019-02
• Subjects: MOS metal-oxide-semiconductor -- FETs field-effect-transistors -- SCEs short-channel effects -- Ion on-state current -- HT high temperature -- I/I ion implantation -- RT room temperature -- Ext. extension -- SD source and drain -- Phos. Phosphorus -- Si:P Phosphorus in-situ doped Si -- NMOS n-type MOS -- B Boron -- SiGe:B Boron in-situ doped SiGe -- PMOS p-type MOS -- RTA rapid thermal annealing -- SIMS secondary ion mass spectrometry -- Rs sheet resistance -- SADP self-aligned double patterning -- STI shallow trench isolation -- DIBL drain-induced-barrier-lowering -- Vd drain voltage -- Lg gate length -- Ron on-state resistance -- Vg gate voltage -- Vth_lin threshold voltage in linear region -- Ioff off-state current -- SSRM scanning spreading resistance microscopy -- TEM transmission electron microscope; Bulk Si fin field-effect-transistors -- High temperature ion implantation -- Phosphorus -- Diffusion -- Drain-induced-barrier-lowering -- On-state current -- Off-state current; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2018.11.003
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlight: We demonstrated n-type bulk Si fin field-effect-transistors by using high temperature Phosphorus extension ion implantation process. In the case of wide spacers and ion implanted Si source and drain, on-state resistance, drain-induced-barrier-lowering, on-state current, and off-state current were improved. In the case of narrow spacers and Phosphorus in-situ doped Si epi source and drain, drain-induced-barrier-lowering and off-state current characteristics were significantly improved. Impurity distribution in channel area was analyzed by scanning spread resistance microscope, and high temperature ion implantation process showed less Phosphorus diffusion. Abstract: In this paper, high temperature Phosphorus ion implantation is applied to p-type Si (1 0 0) substrates and n-type bulk Si fin field-effect-transistors. Phosphorus profiles and sheet resistance on p-type Si (1 0 0) substrates are analyzed. High temperature ion implantation shows less Phosphorus diffusion after rapid thermal annealing compared to room temperature ion implantation. In n-type bulk Si fin field-effect-transistors with wide spacers and ion implanted source and drain, the high temperature extension ion implantation shows better electrical characteristics in terms of drain-induced-barrier-lowering, on-state resistance, on-state current, and off-state current. In n-type bulk Si fin field-effect-transistors with narrow spacers and Phosphorus in-situ doped Si epi source and drain, drain-induced-barrier-lowering and off-state current characteristics are improved by high temperature extension ion implantation, compared to room temperature extension ion implantation. Phosphorus distribution in fin field-effect-transistors is analyzed by scanning spreading resistance microscopy. Suppression of Phosphorus diffusion into the channel area is confirmed.