Design and implementation of a low cost test bench to assess the reliability of FPGA. Issue 9 (August 2015)

• Record Type: Journal Article
• Authors: Naouss, M.; Marc, F.
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 9/10(2015)
• Page Start: 1341
• Page End: 1345
• Publication Date: 2015-08
• Subjects: FPGA -- Reliability -- CMOS -- VLSI; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.06.087
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: One of the challenges of Very Large Scale Integration (VLSI) technology is the high cost of reliability characterization of digital integrated circuit. Benefits from the latest downscaling technology and the exibility of the Field Programmable Gate Array (FPGA) architecture, allow developing a new low cost test bench to assess reliability depending on the operation condition. This work explains how we developed a low cost test bench which can be implemented on up to 32 FPGAs and monitored in real time by a supervisory software. We carried out different stress type tests of Look-up tables (LUTs) on modern FPGA devices and obtained a useful characterization of the LUT aging processes.