Test setup for reliability studies of DDR2 SDRAM. Issue 9 (August 2015)

• Record Type: Journal Article
• Authors: Versen, M.; Ernst, W.; Singh, G.; Gulati, P.
• Is Part Of: Microelectronics and reliability. Volume 55:Issue 9/10(2015)
• Page Start: 1395
• Page End: 1399
• Publication Date: 2015-08
• Subjects: DRAM retention solder simulation; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2015.06.028
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: A DDR2 DRAM test setup is developed and implemented on the Griffin III ATE test system from HILEVEL Technologies. The test system provides a raw platform for performing various mixed signal and digital tests. In order to configure patterns easily in a vector format, a software platform is developed to manage test patterns according to the user's analysis needs. As examples, retention test patterns with disabled self-refresh are applied to 2 Gbit DDR2 SDRAM of two different DRAM vendors. The devices are characterized in respect to their intrinsic leakage and data retention behavior under the influence of stress conditions such as temperature or access algorithm. The tests are automated and test data is logged for an off-line data analysis. Data is recorded before and after solder simulation steps in order to observe a retention time degradation. Highlights: Retention tests with disabled self-refresh are applied to DDR2 SDRAM before and after solder simulation to observe retention time degradation. Memory test vector generation and test setup for the vector based Griffin III Tester of HILEVEL Technologies. Data Analysis with Weibull fail distribution fit.