Cite
HARVARD Citation
Lv, F. et al. (2018). A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications. Microelectronics journal. pp. 36-45. [Online].
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Lv, F. et al. (2018). A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications. Microelectronics journal. pp. 36-45. [Online].