A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications. (December 2018)

• Record Type: Journal Article
• Authors: Lv, Fangxu; Zheng, Xuqiang; Zhao, Feng; Wang, Jianye; Yue, Shigang; Ziqiang Wang, ; Cao, Weidong; He, Yajun; Zhang, Chun; Jiang, Hanjun; Wang, Zhihua
• Is Part Of: Microelectronics journal. Volume 82(2018)
• Page Start: 36
• Page End: 45
• Publication Date: 2018-12
• Subjects: Clock data recovery (CDR) -- Global biasing strategy -- Local clock conditioner -- Phase interpolator (PI) -- Power scaling -- Timing averaging (TA) -- Voltage-controlled delay line (VCDL); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.10.007
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a power scalable clock data recovery (CDR) suitable for multilane and multirate applications. To make the power consumption scale with the data rate and guarantee appropriate edge overlaps for the phase interpolation, a delay-locked loop-based global biasing strategy is proposed to automatically adjust the bandwidth of the current-mode logic buffers and phase interpolator (PI). The I, Q clocks are generated by a local clock conditioner, which employs an open-loop voltage-controlled delay line to produce the evenly spaced multiple phases and adopts a two-stage timing averaging to correct the duty cycle distortion and I, Q mismatch. Additionally, a phase-compensating technique is adopted in the PI to optimize its linearity. Implemented in a 65-nm CMOS process with an area occupation of 0.12 mm 2, the presented CDR can operate from 2 to 10 Gb/s with a scalable power consumption from 11 to 42 mW. When it operates at 10 Gb/s, the maximum tolerable amplitude of the sinusoidal jitter at 50 MHz is 0.52 UIpp, and the total jitter of the recovered clock is 16.6 ps at a BER of 1e-12.