Refined metastability characterization using a time-to-digital converter. (January 2018)

• Record Type: Journal Article
• Authors: Polzer, Thomas; Huemer, Florian; Steininger, Andreas
• Is Part Of: Microelectronics and reliability. Volume 80(2018)
• Page Start: 91
• Page End: 99
• Publication Date: 2018-01
• Subjects: Metastability -- Time-to-digital converter -- TDC -- Late transition detection -- Carry chain; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.11.017
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: In view of the numerous clock domain crossings found in modern systems-on-chip and multicore architectures precise metastability characterization is a fundamental task. We propose a conceptually novel approach for the experimental assessment of upset rate over resolution time that is usually employed to extract the relevant characteristics. Our method is based on connecting a time-to-digital converter to the output of the flip flop under test, rather than using a phase shifted clock, as conventionally done. We present the details of an FPGA implementation of our approach and show its feasibility through an experimental evaluation, whose results favorably match those obtained by the conventional method. The benefits of the novel scheme are the ability to perform a calibration for the delay steps, a speed-up of the measurement process, and the availability of a more comprehensive and ordered measurement data set. Especially the latter can be of crucial importance when (even multiple) glitches or oscillation are suspected to result from metastability, or when the temporal distribution of upsets matters (bursts of upsets, e.g.). Highlights: We have refined the time resolution by a factor of 4. This is a major asset, considering that we are at the border of what is doable. This also resulted in an appreciable change of our implementation. We have largely improved the calibration process, as with the refined resolution we had to deal with non-monotonic behavior of the delay line. In particular we have separated the calibration for rising and falling edges. We have implemented a coding scheme for improving the data transmission from target to host PC. This allowed us to make very comprehensive data collection. Based on all these major refinements we have been able to identify double-glitches in the metastable behavior that have not been reported ever before. Our comparison with reference results from conventional measurements (in the area where those are applicable) confirmed that our approach works with good accuracy.