Estimating dynamic power consumption for memristor-based CiM architecture. (January 2018)

• Record Type: Journal Article
• Authors: Traiola, Marcello; Barbareschi, Mario; Bosio, Alberto
• Is Part Of: Microelectronics and reliability. Volume 80(2018)
• Page Start: 241
• Page End: 248
• Publication Date: 2018-01
• Subjects: Computing-in-Memory architecture -- Power estimation -- Memristor -- Design space exploration -- Boolean functions -- Circuit synthesis; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.12.009
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Nowadays, Computing-in-Memory (CiM) represents one of the most relevant solutions to deal with CMOS technological issues and several works have been proposed so far targeting front and back-end synthesis. However, a given CiM architecture can be synthesized depending on different parameters, leading to different implementations w.r.t. area, power consumption and performance. It is thus mandatory to have an evaluation framework to characterize the actual implementation depending on the above terms. This is even more important during the Design Exploration phase, in which many different implementations are explored to identify the best candidate w.r.t. the user requirements. In this work, we focus on the dynamic power consumption estimation of a given CiM implementation. Instead of resorting to a simulation-based power estimation, we propose an analytical approach that will dramatically speed up the estimation since no simulations are required. By comparing the proposed approach against the simulation-based method over a massive experimental campaign, we show that the accuracy of the estimation turns out to be very high. Highlights: A dynamic power estimation for a memristor-based crossbar architecture is proposed. The estimation relies on a structural analysis of the crossbar(s). A comprehensive description of the algorithm is provided. A comparison w.r.t. the state-of-the-art is included. A comprehensive set of experiments has been carried out.