A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. (1st January 2013)

• Record Type: Journal Article
• Authors: Mehrabani, Yavar Safaei; Zareei, Zahra; Khademzadeh, Ahmad
• Is Part Of: International journal of high performance systems architecture. Volume 4:Number 4(2013)
• Page Start: 196
• Page End: 203
• Publication Date: 2013-01-01
• Subjects: carbon nanotube field effect transistor -- CNFET -- multi-threshold -- nanoelectronics -- full adder -- reliable; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

In this paper a novel carbon nanotube field effect transistor-based (CNFET) one bit full adder cell is presented for low voltage applications. Since in CNFET technology the threshold voltage ( Vth ) of each transistor can be easily changed by the alteration of the diameters of its carbon nanotubes (CNTs), a multi-threshold full adder cell is designed in this paper. In order to have accurate comparisons with some classical and state-of-the-art metal-oxide-semiconducting field-effect transistor (MOSFET) and CNFET based designs, comprehensive simulations with respect to various load capacitances, frequencies, and temperatures have been performed. Simulation results confirm the superiority of the proposed design in terms of delay, power consumption, and power-delay product (PDP), against the other ones. Moreover, since the process fluctuations of today's sub-micron technologies are the most important concern, a Monte Carlo transient analysis in the presence of the mismatches of the CNT diameters is performed. This simulation shows that the proposed cell is reliable and functions properly in the presence of the diameter fluctuations of the CNTs.