Design, analysis, and implementation of partial product reduction phase by using wide m:3 (4 ≤ m ≤ 10) compressors. (1st January 2013) - Mehrabi, Shima; Mirzaee, Reza Faghih; Zamanzadeh, Sharareh; Navi, Keivan; Hashemipour, Omid
Compressors play an important role for partial products reduction in the multiplication process. This paper presents a new implementation for the second phase of a 16 × 16-bit multiplier block using wide m:3 compressors such as 8:3, 9:3, and 10:3. Transistor-level and gate-level analysis are conducted to simulate, test, and implement the proposed structures in 90 nm CMOS technology. The proposed structure has 16% higher efficiency compared when only up to 7:3 counters are employed.