A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation. (January 2018)

• Record Type: Journal Article
• Authors: Kim, Tony Tae-Hyoung; Lee, Zhao Chuan; Do, Anh Tuan
• Is Part Of: Solid-state electronics. Volume 139(2018)
• Page Start: 60
• Page End: 68
• Publication Date: 2018-01
• Subjects: Static random access memory (SRAM) -- Bitline sensing -- Data-independent bitline leakage -- MTCMOS; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2017.10.002
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: A novel 9T SRAM cell is proposed for realizing data-independent bitline leakage. A bias control mechanism for enhancing bitline sensing margin is proposed. The proposed control enhances the bitline sensing window. Abstract: Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V.