On the origins of near-surface stresses in silicon around Cu-filled and CNT-filled through silicon vias. (29th March 2016)

• Record Type: Journal Article
• Authors: Zhu, Ye; Ghosh, Kaushik; Li, Hong Yu; Lin, Yiheng; Tan, Chuan Seng; Xia, Guangrui (Maggie)
• Is Part Of: Semiconductor science and technology. Volume 31:Number 5(2016:May)
• Publication Date: 2016-03-29
• Subjects: 3D integrated circuit (IC) -- through silicon via (TSV) -- carbon nanotube (CNT); Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/0268-1242/31/5/055008
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: Micro-Raman spectroscopy was employed to study the near-surface stress distributions and origins in Si around through silicon vias (TSVs) at both room temperature and elevated temperatures for Cu-filled and carbon nanotube (CNT)-filled TSV samples. From observations, we proved that the stresses near TSVs are mainly from two sources: (1) pre-existing stress before via filling, and (2) coefficients of thermal expansion (CTE) mismatch-induced stress. CTE-mismatch-induced stress is shown to dominate the compressive regime of the near-surface stress distribution around the two types of Cu-filled TSV structures in this work and in previous work, while pre-existing stress dominates the full range of the stress distribution in the CNT-filled TSV structures studied. These results show the importance of the pre-existing stress and support the use of a liner technology with lower stress introduction such as deposited oxide instead of thermal oxide. It is specifically important for CNT-filled TSVs, where the pre-existing stress is much larger than the CTE-mismatch-induced stress as observed in this work.