Double-gate junctionless transistor model including short-channel effects. (16th April 2015)

• Record Type: Journal Article
• Authors: Paz, B C; Ávila-Herrera, F; Cerdeira, A; Pavanello, M A
• Is Part Of: Semiconductor science and technology. Volume 30:Number 5(2015:May)
• Publication Date: 2015-04-16
• Subjects: junctionless -- model -- short-channel; Semiconductors -- Periodicals; 621.38152
• DOI: 10.1088/0268-1242/30/5/055011
• Languages: English
• ISSNs: 0268-1242

Abstract

Abstract: This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage ( V TH ), subthreshold slope ( S ) and drain induced barrier lowering.