Lifetime-aware scheduling in high level synthesis. (December 2018)

• Record Type: Journal Article
• Authors: Es'haghi, Siavash; Eshghi, Mohammad
• Is Part Of: Microelectronics and reliability. Volume 91(2018)Part 1
• Page Start: 86
• Page End: 97
• Publication Date: 2018-12
• Subjects: High level synthesis -- Scheduling -- Reliability -- Aging -- Lifetime; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2018.06.016
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Among various reliability challenges, accelerated aging is of particular importance. The flexibility of high-level synthesis (HLS) can be employed at an affordable cost to increase the reliability, and in particular lifetime, of the systems. In this paper, we extract the aging characteristics of the functional units (FUs), then, a scheduling method based on integer linear programming (ILP) is proposed to increase the lifetime, using the aging characteristics of the FUs. The proposed method extends the lifetime beyond the minimum expected value, with the minimum latency overhead, by applying the operation chaining and multicycling techniques in an aging-aware approach. The constraint matrix of the proposed ILP formulation is totally unimodular. This technique is suitable for both data-flow intensive and control-flow intensive designs and is applicable for large circuits. Experimental results show that the proposed approach increases the lifetime by 2.33×, and increases the latency by an average of 19.8%. Highlights: A new aging-aware scheduling to ensure the minimum expected lifetime is designed. The lifetime is extended with minimum latency overhead. Chaining, multicycling and cycle inserting are performed in an aging-aware manner. Suitable for data-flow intensive and control-flow intensive designs Applicable for large circuits