Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22 nm node pMOSFETs. (December 2015)

• Record Type: Journal Article
• Authors: Wang, Guilei; Moeen, M.; Abedin, A.; Xu, Yefeng; Luo, Jun; Guo, Yiluan; Qin, Changliang; Tang, Zhaoyun; Yin, Haizhou; Li, Junfeng; Yan, Jiang; Zhu, Huilong; Zhao, Chao; Chen, Dapeng; Ye, Tianchun; Kolahdouz, M.; Radamson, Henry H.
• Is Part Of: Solid-state electronics. Volume 114(2015)
• Page Start: 43
• Page End: 48
• Publication Date: 2015-12
• Subjects: CMOS -- SiGe -- Selective epitaxy -- RPCVD; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.07.003
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Selective epitaxy SiGe growth in recessed S/D regions of 22 nm pMOSFETs was investigated. The profile of SiGe layers and strain distribution of Ni silicide formation were simulated. Pattern dependency of SiGe selective growth was calculated. The interaction between chips over the entire 8-in. wafer was determined. Abstract: Pattern dependency of selective epitaxy of Si1 − x Ge x (0.20 ⩽ x ⩽ 0.45) grown in recessed source/drain regions of 22 nm pMOSFETs has been studied. A complete substrate mapping over 200 mm wafers was performed and the transistors' characteristics were measured. The designed SiGe profile included a layer with Ge content of 40% at the bottom of recess (40 nm) and capped with 20% Ge as a sacrificial layer (20 nm) for silicide formation. The induced strain in the channel was simulated before and after silicidation. The variation of strain was localized and its effect on the transistors' performance was determined. The chips had a variety of SiGe profile depending on their distance (closest, intermediate and central) from the edge of the 200 mm wafer. SiGe layers with poor epi-quality were observed when the coverage of exposed Si of the chip was below 1%. This causes high Ge contents with layer thicknesses above the critical thickness.