Replacement fin processing for III–V on Si: From FinFets to nanowires. (January 2016)

• Record Type: Journal Article
• Authors: Waldron, Niamh; Merckling, Clement; Teugels, Lieve; Ong, Patrick; Sebaai, Farid; Barla, Kathy; Collaert, Nadine; Thean, Voon-Yew (Aaron)
• Is Part Of: Solid-state electronics. Volume 115 Part B(2016)
• Page Start: 81
• Page End: 91
• Publication Date: 2016-01
• Subjects: III-V -- FinFet -- Gate-All-Around (GAA) -- Nanowire -- InGaAs -- MOS; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.09.020
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: In this paper we review the details and results of the replacement fin process technique used to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300 mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the performance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with LG = 60 nm have a peak transconductance of 1030 μS/μm with a SSSAT of 125 mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high-k interface. Nanowires with a diameter of 6 nm were demonstrated to show quantization induced immunity to D it resulting in a SSSAT as low as 66 mV/dec for 85 nm LG devices.