Conduction barrier offset engineering for DRAM capacitor scaling. (January 2016)

• Record Type: Journal Article
• Authors: Pešić, Milan; Knebel, Steve; Cho, Kyuho; Jung, Changhwa; Chang, Jaewan; Lim, Hanjin; Kolomiiets, Nadiia; Afanas'ev, Valeri V.; Mikolajick, Thomas; Schroeder, Uwe
• Is Part Of: Solid-state electronics. Volume 115 Part B(2016)
• Page Start: 133
• Page End: 139
• Publication Date: 2016-01
• Subjects: Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2015.08.012
• Languages: English
• ISSNs: 0038-1101

Abstract

Abstract: DRAM capacitors are reaching the scaling limit and new approaches are necessary to enable further reduction of the physical thickness of the capacitor dielectric. The conduction band offset (CBO) of a platinum noble metal electrode on atomic layer deposited ZrO2 /Al2 O3 /ZrO2 is evaluated and compared to a titanium nitride electrode. Internal Photo Emission Spectroscopy and Photoconductivity measurement are used to estimate the barrier height and band gap, respectively. The barrier height difference between the two electrodes is evaluated in comparison with a previously reported model. Finally, the impact of an increased barrier height on dielectric scaling will be discussed based on a leakage current simulation of a ZrO2 capacitor.