Half-Corbino short-channel amorphous In–Ga–Zn–O thin-film transistors with a-SiOx or a-SiOx/a-SiNx passivation layers. (June 2016)

• Record Type: Journal Article
• Authors: Zhao, Chumin; Fung, Tze-Ching; Kanicki, Jerzy
• Is Part Of: Solid-state electronics. Volume 120(2016)
• Page Start: 25
• Page End: 31
• Publication Date: 2016-06
• Subjects: Thin-film transistors -- Amorphous In–Ga–Zn–O -- Corbino -- Asymmetric electrical properties -- Short-channel effect -- Bias-temperature stability; Semiconductors -- Periodicals; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.sse.2016.03.003
• Languages: English
• ISSNs: 0038-1101

Abstract

Highlights: Half-Corbino a-IGZO TFTs with a-SiO x and a-SiO x /a-SiN x passivation layers are fabricated. Short-channel effect of half-Corbino a-IGZO TFT leads to asymmetric electrical properties. The impact of Mo/a-IGZO contacts on device properties is discussed. The origins of threshold voltage shift during bias temperature stress are studied. Electrical stability is improved using the a-SiO x /a-SiN x bilayer passivation structure. Abstract: We investigated the electrical properties and stability of short-channel half-Corbino amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs). In the linear region, the fabricated half-Corbino a-IGZO TFT with a channel length of 4.5 μm achieves a geometrical factor ( f g ) of ∼2.7, a threshold voltage ( V T ) of ∼2.4 V, a field-effect mobility ( μ eff ) of ∼15 cm 2 /Vs, a subthreshold swing ( SS ) of ∼320 mV/dec and an off-current ( I OFF ) < 10 −13 A. In the saturation region, asymmetric electrical characteristics such as drain current were observed under different drain bias conditions. The electrical properties asymmetry of half-Corbino a-IGZO TFTs was explained by various geometrical factors owing to the short-channel effect. The reduced V T and increased SS at V DS = 15 V is explained by the drain-induced Schottky barrier lowering. In addition, the bias-temperature stress (BTS) was performed for half-Corbino a-IGZO TFTs with both amorphous silicon oxide (a-SiO x ) single layer and a-SiO x /amorphous silicon nitride (a-SiN x ) bilayer passivation (PV) structures. The device with bilayer PV shows a threshold voltage shift (Δ V T ) of +2.07 and −0.5 V under positive (PBTS = +15 V) and negative BTS (NBTS = −15 V) at 70 °C for 10 ks, respectively. The origins of Δ V T during PBTS and NBTS for half-Corbino a-IGZO TFTs with single and bilayer PV structures were studied. To improve the device electrical stability, the bilayer PV structure should be used.