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APA Citation
Kavitha, A., & SasiKumar, S. (2015). a novel two-fold state skip logic Built-In Self-Test scheme for digital circuits. Computers & electrical engineering, 48, 239–246. http://access.bl.uk/ark:/81055/vdc_100041337188.0x000052
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Kavitha, A., & SasiKumar, S. (2015). a novel two-fold state skip logic Built-In Self-Test scheme for digital circuits. Computers & electrical engineering, 48, 239–246. http://access.bl.uk/ark:/81055/vdc_100041337188.0x000052