4H-SiC trench MOSFET with splitting double-stacked shielded region. (October 2018)

• Record Type: Journal Article
• Authors: Yang, Tongtong; Bai, Song; Huang, Runhua
• Is Part Of: Superlattices and microstructures. Volume 122(2018)
• Page Start: 419
• Page End: 425
• Publication Date: 2018-10
• Subjects: Silicon Carbide -- Metal oxide semiconductor field effect transistor -- Sentaurus tcad simulations -- Switching loss -- Gate charge; Superlattices as materials -- Periodicals; Microstructure -- Periodicals; Semiconductors -- Periodicals; Superréseaux -- Périodiques; Microstructure (Physique) -- Périodiques; Semiconducteurs -- Périodiques; 621.38152
• DOI: 10.1016/j.spmi.2018.06.069
• Languages: English
• ISSNs: 0749-6036

Abstract

Abstract: A Silicon Carbide(SiC) MOSFET with double–stacked shielded region beneath the trench bottom(DSS-MOS) is presented and investigated through Sentaurus TCAD simulations. The proposed structure introduces additional electron conduction path beneath the trench without degradation of shielding effect for the gate oxide. As a result, the DSS-MOS exhibits a higher figure of merit related to the breakdown voltage and specific ON-resistance (VBR 2 /RON ) compared with that of trench MOSFET with L-shaped gate(LSG-MOS). Furthermore, owing to the strong p + shielding effect, the feedback capacitance and the gate-to-drain charge of the DSS-MOS are significantly reduced, thus leading to improved switching performance. We believe that the proposed DSS-MOS could provide an effective solution to improve gate oxide reliability and reduce switching losses for SiC power device operating in high-frequency applications. Highlights: Silicon Carbide trench MOSFET with double-stacked shielded region is reported. Obvious improvement in Figure of Merit(Vbr2/Ron) is achieved. Low gate-drain charge and switching losses are observed.