DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs. (August 2016)

• Record Type: Journal Article
• Authors: Reviriego, P.; Demirci, M.; Tabero, J.; Regadío, A.; Maestro, J.A.
• Is Part Of: Microelectronics and reliability. Volume 63(2016)
• Page Start: 314
• Page End: 318
• Publication Date: 2016-08
• Subjects: FPGA -- Error correction -- Fault tolerance; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2016.06.019
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: Registers are one of the circuit elements that can be affected by soft errors. To ensure that soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is commonly used to protect registers. TMR can effectively protect against errors affecting a single flip-flop and has a low overhead in terms of circuit delay. The main drawback of TMR is that it requires more than three times the original circuit area as the flip-flops are triplicated and additional voting logic is inserted. Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations. In this paper, DMR + an alternative to TMR to protect registers in FPGAs, is presented. The proposed scheme exploits the FPGA structure to achieve a reduction in the FPGA resources (LUTs and Flip-Flops) at the cost of a certain overhead in delay. DMR + can correct all single bit errors like TMR but is more vulnerable to multiple bit errors. To evaluate the benefits, the DMR + technique has been implemented and compared with TMR considering standalone registers and also some simple designs. Highlights: DMR + an alternative to TMR to protect Flip-Flops in Xilinx FPGAs is presented. DMR + reduces the overheads needed to protect Flip-Flops in Xilinx FPGAs. DMR + is evaluated for some simple blocks and two case study designs to show its benefits.