Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs. (August 2016)

• Record Type: Journal Article
• Authors: Garegnani, Giacomo; Fiori, Vincent; Gouget, Gilles; Monsieur, Frederic; Tavernier, Clement
• Is Part Of: Microelectronics and reliability. Volume 63(2016)
• Page Start: 90
• Page End: 96
• Publication Date: 2016-08
• Subjects: Nano-scale MOSFETs -- Self-heating -- Temperature measurements -- FEM simulations -- Correlation analysis -- Thermal sensors; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2016.03.007
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation results show temperature elevations up to approximately 120 K in the hot spot, 70 K in the gate and 7 K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical parameters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measurements confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design. Highlights: We successfully investigate the dependence of self-heating on geometry. We balance the effect of various parameters in the simulation set up. At wafer level, BEoL and contacts do not have an impact on self-heating effects. Precise and light thermal models, create a practical tool for reliability analysis. Good correlation between simulations and measurements validates the model.